#include "StdAfx.h"
#include "deadZ80.h"
#include "opcodes.h"

int CDeadZ80::ExecuteOpcodeDD()
{
	unsigned char opcode = ReadMemory8(pc++);
	unsigned short stmp;
	unsigned char tmp,tmp2;
	unsigned long ltmp;

#define IXd()	\
	(unsigned long)(unsigned short)((signed short)IX + (signed char)ReadMemory8(pc++))

	switch(opcode) {
		case 0x09:	ADD16(IX,BC);				cycles += 7;	break;
		case 0x19:	ADD16(IX,DE);				cycles += 7;	break;
		case 0x21:	IX = ReadMemory16(pc);pc += 2;cycles += 14;	break;
		case 0x22:	WriteMemory16(ReadMemory16(pc),IX);pc += 2;cycles += 14;	break;
		case 0x23:	IX++;						cycles += 10;	break;
		case 0x24:	INC(IXH);					cycles += 10;	break;
		case 0x25:	DEC(IXH);					cycles += 10;	break;
		case 0x26:	IXH = ReadMemory8(pc++);	cycles += 10;	break;
		case 0x29:	ADD16(IX,IX);				cycles += 6;	break;
		case 0x39:	ADD16(IX,sp);				cycles += 7;	break;
		case 0x2A:	IX = ReadMemory16(ReadMemory16(pc));pc += 2;cycles += 14;	break;
		case 0x2B:	IX--;						cycles += 10;	break;
		case 0x2C:	INC(IXL);					cycles += 10;	break;
		case 0x2D:	DEC(IXL);					cycles += 10;	break;
		case 0x2E:	IXL = ReadMemory8(pc++);	cycles += 10;	break;
		case 0x34:	//inc (IX+d)
			ltmp = IXd();
			tmp = ReadMemory8(ltmp);
			INC(tmp);
			WriteMemory8(ltmp,tmp);
			cycles += 19;
			break;

		case 0x35:	//dec (IX+d)
			ltmp = IXd();
			tmp = ReadMemory8(ltmp);
			DEC(tmp);
			WriteMemory8(ltmp,tmp);
			cycles += 19;
			break;

		case 0x36:	ltmp = IXd();WriteMemory8(ltmp,ReadMemory8(pc++));cycles += 19;break;	//ld (IX+d),n
		case 0x40:	B = B;								cycles += 4;	break;
		case 0x41:	B = C;								cycles += 4;	break;
		case 0x42:	B = D;								cycles += 4;	break;
		case 0x43:	B = E;								cycles += 4;	break;
		case 0x44:	B = IXH;							cycles += 4;	break;
		case 0x45:	B = IXL;							cycles += 4;	break;
		case 0x46:	B = ReadMemory8(IXd());				cycles += 19;	break;	//ld b,(IX+d)
		case 0x47:	B = A;								cycles += 4;	break;
		case 0x48:	C = B;								cycles += 4;	break;
		case 0x49:	C = C;								cycles += 4;	break;
		case 0x4A:	C = D;								cycles += 4;	break;
		case 0x4B:	C = E;								cycles += 4;	break;
		case 0x4C:	C = IXH;							cycles += 4;	break;
		case 0x4D:	C = IXL;							cycles += 4;	break;
		case 0x4E:	C = ReadMemory8(IXd());				cycles += 19;	break;	//ld c,(IX+d)
		case 0x4F:	C = A;								cycles += 4;	break;
		case 0x50:	D = B;								cycles += 4;	break;
		case 0x51:	D = C;								cycles += 4;	break;
		case 0x52:	D = D;								cycles += 4;	break;
		case 0x53:	D = E;								cycles += 4;	break;
		case 0x54:	D = IXH;							cycles += 4;	break;
		case 0x55:	D = IXL;							cycles += 4;	break;
		case 0x56:	D = ReadMemory8(IXd());				cycles += 19;	break;	//ld d,(IX+d)
		case 0x57:	D = A;								cycles += 4;	break;
		case 0x58:	E = B;								cycles += 4;	break;
		case 0x59:	E = C;								cycles += 4;	break;
		case 0x5A:	E = D;								cycles += 4;	break;
		case 0x5B:	E = E;								cycles += 4;	break;
		case 0x5C:	E = IXH;							cycles += 4;	break;
		case 0x5D:	E = IXL;							cycles += 4;	break;
		case 0x5E:	E = ReadMemory8(IXd());				cycles += 19;	break;	//ld e,(IX+d)
		case 0x5F:	E = A;								cycles += 4;	break;
		case 0x60:	H = B;								cycles += 4;	break;
		case 0x61:	H = C;								cycles += 4;	break;
		case 0x62:	H = D;								cycles += 4;	break;
		case 0x63:	H = E;								cycles += 4;	break;
		case 0x64:	H = IXH;							cycles += 4;	break;
		case 0x65:	H = IXL;							cycles += 4;	break;
		case 0x66:	H = ReadMemory8(IXd());				cycles += 19;	break;	//ld h,(IX+d)
		case 0x67:	H = A;								cycles += 4;	break;
		case 0x68:	L = B;								cycles += 4;	break;
		case 0x69:	L = C;								cycles += 4;	break;
		case 0x6A:	L = D;								cycles += 4;	break;
		case 0x6B:	L = E;								cycles += 4;	break;
		case 0x6C:	L = IXH;							cycles += 4;	break;
		case 0x6D:	L = IXL;							cycles += 4;	break;
		case 0x6E:	L = ReadMemory8(IXd());				cycles += 19;	break;	//ld l,(IX+d)
		case 0x6F:	L = A;								cycles += 4;	break;
		case 0x70:	WriteMemory8(IXd(),B);				cycles += 19;	break;	//ld (IX+d),b
		case 0x71:	WriteMemory8(IXd(),C);				cycles += 19;	break;	//ld (IX+d),c
		case 0x72:	WriteMemory8(IXd(),D);				cycles += 19;	break;	//ld (IX+d),d
		case 0x73:	WriteMemory8(IXd(),E);				cycles += 19;	break;	//ld (IX+d),e
		case 0x74:	WriteMemory8(IXd(),H);				cycles += 19;	break;	//ld (IX+d),h
		case 0x75:	WriteMemory8(IXd(),L);				cycles += 19;	break;	//ld (IX+d),l
		case 0x77:	WriteMemory8(IXd(),A);				cycles += 19;	break;	//ld (IX+d),a
		case 0x78:	A = B;								cycles += 4;	break;
		case 0x79:	A = C;								cycles += 4;	break;
		case 0x7A:	A = D;								cycles += 4;	break;
		case 0x7B:	A = E;								cycles += 4;	break;
		case 0x7C:	A = IXH;							cycles += 4;	break;
		case 0x7D:	A = IXL;							cycles += 4;	break;
		case 0x7E:	A = ReadMemory8(IXd());				cycles += 19;	break;	//ld a,(IX+d)
		case 0x7F:	A = A;								cycles += 4;	break;
		case 0x84:	ADD(IXH);							cycles += 9;	break;
		case 0x85:	ADD(IXL);							cycles += 9;	break;
		case 0x86:	tmp2=ReadMemory8(IXd());ADD(tmp2);	cycles += 19;	break;	//add a,(IX+d)
		case 0x8C:	ADC(IXH);							cycles += 9;	break;
		case 0x8D:	ADC(IXL);							cycles += 9;	break;
		case 0x8E:	tmp2=ReadMemory8(IXd());ADC(tmp2);	cycles += 19;	break;	//adc a,(IX+d)
		case 0x94:	SUB(IXH);							cycles += 9;	break;
		case 0x95:	SUB(IXL);							cycles += 9;	break;
		case 0x96:	tmp2=ReadMemory8(IXd());SUB(tmp2);	cycles += 19;	break;	//sub a,(IX+d)
		case 0x9C:	SBC(IXH);							cycles += 9;	break;
		case 0x9D:	SBC(IXL);							cycles += 9;	break;
		case 0x9E:	tmp2=ReadMemory8(IXd());SBC(tmp2);	cycles += 19;	break;	//sbc a,(IX+d)
		case 0xA4:	AND(IXH);							cycles += 9;	break;
		case 0xA5:	AND(IXL);							cycles += 9;	break;
		case 0xA6:	tmp2=ReadMemory8(IXd());AND(tmp2);	cycles += 19;	break;
		case 0xAC:	XOR(IXH);							cycles += 9;	break;
		case 0xAD:	XOR(IXL);							cycles += 9;	break;
		case 0xAE:	tmp2=ReadMemory8(IXd());XOR(tmp2);	cycles += 19;	break;
		case 0xB4:	OR(IXH);							cycles += 9;	break;
		case 0xB5:	OR(IXL);							cycles += 9;	break;
		case 0xB6:	tmp2=ReadMemory8(IXd());OR(tmp2);	cycles += 19;	break;
		case 0xBC:	CP(IXH);							cycles += 9;	break;
		case 0xBD:	CP(IXL);							cycles += 9;	break;
		case 0xBE:	tmp2=ReadMemory8(IXd());CP(tmp2);	cycles += 19;	break;
		case 0xCB:	return(ExecuteOpcodeDDCB());
		case 0xE1:	POP16(IX);											break;	//pop IX
		case 0xE5:	PUSH16(IX);							cycles += 11;	break;	//push IX
		default:	message("bad DD opcode $%02X\n",opcode);			return(1);
	}
	return(0);
}
